Browse and filter these roles on Hiring Tempo →- Memory Design EngineerIntel · US, Oregon, Hillsboro; US, California, Santa Clara; US, Texas, Austin · posted 2026-11-05NEW
- ASIC Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-11-04NEW
- Distinguished Platform EngineerServiceNow · Santa Clara, CALIFORNIA, United States · posted 2026-11-03NEW
- RF PDK DRC Development Engineer - Design EnablementGlobalFoundries · Santa Clara; USA - New York - Malta · posted 2026-11-03NEW
- Senior DFT Design EngineerIntel · US, California, Folsom; US, Oregon, Hillsboro; US, California, Santa Clara +1 more · posted 2026-11-03NEW
- Senior Digital Design EngineerNVIDIA · US, CA, Santa Clara; US, TX, Austin; US, WA, Redmond · posted 2026-11-03NEW
- Senior AI-Native Designer & Builder, Design SystemZscaler · Santa Clara, California, USA · posted 2026-11-03NEW
- Physical Design Clocking EngineerIntel · US, California, Santa Clara · posted 2026-11-03NEW
- Senior Mask Design Engineer - HardwareNVIDIA · US, CA, Santa Clara · posted 2026-11-02NEW
- Package Design, Signal and Power Integrity Senior Staff EngineerMarvell · Santa Clara, CA · posted 2026-11-02NEW
- Design Technology Platform Executive AdminIntel · US, California, Santa Clara · posted 2026-11-02NEW
- Sr Director, XSE Design Verification EngineeringIntel · US, California, Santa Clara · posted 2026-11-02NEW
- Distinguished Engineer, Power ArchitectureNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Software R&D Engineer, VLSI Physical DesignNVIDIA · US, CA, Santa Clara; US, TX, Austin · posted 2026-10-30
- Senior ASIC Physical Design Engineer, Cache Coherent InterconnectsNVIDIA · US, CA, Santa Clara; US, OR, Hillsboro · posted 2026-10-30
- Senior Mask Design Engineer - HardwareNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Manager, Digital Design - Mixed-Signal High-Speed I/O SerDesNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mask Design Engineer - HardwareNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Circuit Methodology EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mixed Signal Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Linux Software Engineer - Chip System SoftwareNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Applied AI Engineer - VLSI DesignNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mask Design Engineer - HardwareNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mixed Signal Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- EDA Tools & Design Automation Engineer Tenstorrent · Santa Clara, California, United States · posted 2026-10-30NEW
- Senior Circuit Design Engineer - PowerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- ASIC Design Engineer - New College Grad 2026NVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Mechanical Design EngineerApplied Materials · Santa Clara,CA · posted 2026-10-30
- Senior Logic Design Engineer, Cache Coherent InterconnectsNVIDIA · US, CA, Santa Clara; US, OR, Hillsboro · posted 2026-10-30
- Senior Mixed Signal Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mixed Signal Design Validation EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Software R&D Engineer, VLSI Physical DesignNVIDIA · US, CA, Santa Clara; US, TX, Austin · posted 2026-10-30
- Distinguished Engineer, End-to-End Scaling Performance ArchitectureNVIDIA · US, CA, Santa Clara; US, TX, Austin; US, WA, Redmond · posted 2026-10-30
- Tech Engagement Lead - Model BuilderNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior ASIC Floorplan Design EngineerNVIDIA · US, CA, Santa Clara; US, TX, Austin · posted 2026-10-30
- Senior Mixed Signal Design Validation EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Lead Hardware Design Validation EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mask Design Engineer - HardwareNVIDIA · US, CA, Santa Clara; US, CA, Remote · posted 2026-10-30
- Senior Physical Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Thermal Mechanical Photonic DesignerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Solutions Architect, LLM Model BuilderNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Manager, System Design Tools and MethodologyNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior ASIC Design Verification Infrastructure and Tools Engineer – GPUNVIDIA · US, CA, Santa Clara; US, MA, Westford; US, TX, Austin +2 more · posted 2026-10-30
- Senior Mixed Signal Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Digital Design Verification Engineer - HardwareNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mixed Signal Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Applied Research Engineer, Chip DesignNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Research Scientist, CircuitsNVIDIA · US, CA, Santa Clara; US, NC, Durham · posted 2026-10-30
- Principal Thermal Mechanical Photonic DesignerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mixed Signal Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Circuit Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Global Connectivity Distinguished EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mixed Signal Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Lead Hardware Design Validation Engineer - Memory SubsystemNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Liquid-Cooling Specialist - DatacenterNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Enterprise AV Design and Collaboration EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- ASIC Physical Design and Timing Engineer - New College Grad 2026NVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Hardware Design Validation Engineer - Memory SubsystemNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mixed-Signal Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Mixed Signal Design Validation EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior ASIC Design Engineer - Agentic AINVIDIA · US, CA, Santa Clara; US, TX, Austin; US, NC, Durham · posted 2026-10-30
- Senior Mixed Signal Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Software Engineer — cuEquivarianceNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Supplier Base Engineer – Liquid Cooling Contamination ControlNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mask Design Engineer - HardwareNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mask Design Engineer - HardwareNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Distinguished Engineer - Wireless InfrastructureNVIDIA · US, CA, Santa Clara; US, NH, Remote; US, MA, Remote · posted 2026-10-30
- Senior Circuit Design Engineer - Power Modeling and SimulationNVIDIA · US, CA, Santa Clara; US, CA, Remote · posted 2026-10-30
- Distinguished Engineer, Scaled Out InferencingNVIDIA · US, CA, Santa Clara; US, CA, Remote · posted 2026-10-30
- Senior Mixed Signal Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Design Engineer, Coherent High Speed InterconnectNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Digital Design Engineer - High-Speed I/O and PhotonicsNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mixed Signal Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Digital Design EngineerNVIDIA · US, CA, Santa Clara; US, TX, Austin; US, WA, Redmond · posted 2026-10-30
- Principal Photonics IC Design EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Senior Mask Layout Design EngineerNVIDIA · US, CA, Santa Clara; US, CA, Remote · posted 2026-10-30
- Circuit Design Engineer - Standard CellNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- Photonic Mixed Signal Design Validation EngineerNVIDIA · US, CA, Santa Clara · posted 2026-10-30
- GPU Logic Design EngineerIntel · US, California, Folsom; US, California, Santa Clara · posted 2026-10-29
- ASIC Physical Design Engineer, Netlisting - New College Grad 2026NVIDIA · US, CA, Santa Clara; US, TX, Austin · posted 2026-10-29
- Senior Principal Engineer, Physical DesignerMarvell · Santa Clara, CA · posted 2026-10-29
- Sr. Staff Design Strategist, Customer EnablementServiceNow · Santa Clara, California, United States · posted 2026-10-28
- Senior SRAM Engineer, Circuit DesignNVIDIA · US, CA, Santa Clara; US, TX, Austin; US, TX, Remote +1 more · posted 2026-10-28
- Design Automation Engineer (TFM/EDA)Intel · US, California, Folsom; US, Oregon, Hillsboro; US, California, Santa Clara +1 more · posted 2026-10-28
- Design Automation Engineer (TFM/EDA)Intel · US, California, Folsom; US, Oregon, Hillsboro; US, California, Santa Clara +1 more · posted 2026-10-28
- Senior Physical Design Methodology Engineer, PPA Improvement Technology ScalingNVIDIA · US, CA, Santa Clara; US, TX, Austin · posted 2026-10-28
- CryoCMOS Design Director, QuantumGlobalFoundries · Austin; Santa Clara · posted 2026-10-28
- GPU Design Verification EngineerIntel · US, California, Folsom; US, California, Santa Clara · posted 2026-10-27
- Research Scientist, Electronic Design Automation - New College Grad 2026NVIDIA · US, CA, Santa Clara · posted 2026-10-27
- Senior Principal Linux Kernel EngineerOracle · Santa Clara, CA, United States; Seattle, WA, United States; United States · posted 2026-10-27
- Mechanical Design Engineer (ESC) IVApplied Materials · Santa Clara,CA · posted 2026-10-27
- GPU Design Verification EngineerIntel · US, California, Folsom; US, California, Santa Clara · posted 2026-10-27
- CPU IP Design & Verification Intern – RISC-V Processor Development (Summer 2027)GlobalFoundries · USA - Texas - Austin; USA - California - Santa Clara · posted 2026-10-23
- CPU IP Design & Verification Engineer – RISC-V (2027 New College Graduate)GlobalFoundries · USA - Texas - Austin; USA - California - Santa Clara · posted 2026-10-23
- Design Verification EngineerIntel · US, California, Santa Clara; US, Texas, Austin · posted 2026-10-22
- Senior Principal Engineer, Hardware Application Engineering — Board & System DesignMarvell · Santa Clara, CA · posted 2026-10-22
- Silicon Co-Design Engineer - New College Grad 2026NVIDIA · US, CA, Santa Clara · posted 2026-10-22
- Senior Software Engineer, Virtualization and Linux KernelNVIDIA · US, CA, Santa Clara; US, CO, Remote · posted 2026-10-22
- Hardware/Design Engineer: RoboticsApplied Materials · Santa Clara,CA · posted 2026-10-22
- Microarchitecture and Design Engineer - AI SoCIntel · US, California, Santa Clara; US, California, Folsom · posted 2026-10-21
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