Browse and filter these roles on Hiring Tempo →- Memory Design EngineerIntel · US, Oregon, Hillsboro; US, California, Santa Clara; US, Texas, Austin · posted 2026-11-05NEW
- Mechanical Design EngineerNeuralink · Austin, Texas, United States · posted 2026-11-05NEW
- Design Engineering Architect – Systems and InterfacesCadence · SAN JOSE; AUSTIN · posted 2026-11-04NEW
- Product DesignerTrimble · US - GA, Alpharetta; US - TX, Austin · posted 2026-11-03NEW
- Private Equity Practice LeadOracle · United States; Denver, CO, United States; Austin, TX, United States +5 more · posted 2026-11-03NEW
- Product DesignerTrimble · US - TX, Austin; US - GA, Atlanta · posted 2026-11-03NEW
- Senior Digital Design EngineerNVIDIA · US, CA, Santa Clara; US, TX, Austin; US, WA, Redmond · posted 2026-11-03NEW
- Private Equity Practice LeadOracle · United States; Denver, CO, United States; Austin, TX, United States +5 more · posted 2026-11-03NEW
- Memory Design EngineerIntel · US, Texas, Austin · posted 2026-11-02NEW
- PVD Equipment Technician- Nights 2NXP Semiconductors · Austin (Ed Bluestein, Manufacturing) · posted 2026-11-02NEW
- Staff Design Verification Engineer – SoC and eFPGAAnalog Devices · US, TX, Austin, Plaza on the Lake · posted 2026-11-02NEW
- Senior Software R&D Engineer, VLSI Physical DesignNVIDIA · US, CA, Santa Clara; US, TX, Austin · posted 2026-10-30
- Senior Software R&D Engineer, VLSI Physical DesignNVIDIA · US, CA, Santa Clara; US, TX, Austin · posted 2026-10-30
- Distinguished Engineer, End-to-End Scaling Performance ArchitectureNVIDIA · US, CA, Santa Clara; US, TX, Austin; US, WA, Redmond · posted 2026-10-30
- Senior ASIC Floorplan Design EngineerNVIDIA · US, CA, Santa Clara; US, TX, Austin · posted 2026-10-30
- Senior Design Engineer - Electromagnetic (R&D)Apptronik · Austin, TX · posted 2026-10-30NEW
- ASIC Design Verification Engineer - New College Grad 2026NVIDIA · US, TX, Austin · posted 2026-10-30
- Senior ASIC Design Verification Infrastructure and Tools Engineer – GPUNVIDIA · US, CA, Santa Clara; US, MA, Westford; US, TX, Austin +2 more · posted 2026-10-30
- Senior CPU Design EngineerNVIDIA · US, OR, Hillsboro; US, MA, Westford; US, TX, Austin +3 more · posted 2026-10-30
- Senior ASIC Design Engineer - Agentic AINVIDIA · US, CA, Santa Clara; US, TX, Austin; US, NC, Durham · posted 2026-10-30
- Senior Digital Design EngineerNVIDIA · US, CA, Santa Clara; US, TX, Austin; US, WA, Redmond · posted 2026-10-30
- Design Application Engineering Intern (Summer 2027)GlobalFoundries · USA - Texas - Austin · posted 2026-10-29
- Forward Deployed Build EngineerSaronic · Austin, TX · posted 2026-10-29
- Senior Photo Equipment TechnicianNXP Semiconductors · Austin (Ed Bluestein, Manufacturing) · posted 2026-10-29
- ASIC Physical Design Engineer, Netlisting - New College Grad 2026NVIDIA · US, CA, Santa Clara; US, TX, Austin · posted 2026-10-29
- CPU Physical Design EngineerIntel · US, Texas, Austin · posted 2026-10-29
- Etch Equipment Engineer - NightsSamsung · 12100 Samsung Blvd, Austin, TX, USA · posted 2026-10-28
- Etch Equipment Technician - DaysSamsung · 12100 Samsung Blvd, Austin, TX, USA · posted 2026-10-28
- Etch Equipment Technician - NightsSamsung · 12100 Samsung Blvd, Austin, TX, USA · posted 2026-10-28
- Senior SRAM Engineer, Circuit DesignNVIDIA · US, CA, Santa Clara; US, TX, Austin; US, TX, Remote +1 more · posted 2026-10-28
- Staff Analog Design EngineerAnalog Devices · US, TX, Austin, Plaza on the Lake; US, NC, Durham · posted 2026-10-28
- Design Application EngineerGlobalFoundries · OFFSITE - USA - California; Essex Junction; Austin +1 more · posted 2026-10-28
- Director, Analog DesignAnalog Devices · US, TX, Austin, Plaza on the Lake · posted 2026-10-28
- Senior Physical Design Methodology Engineer, PPA Improvement Technology ScalingNVIDIA · US, CA, Santa Clara; US, TX, Austin · posted 2026-10-28
- CryoCMOS Design Director, QuantumGlobalFoundries · Austin; Santa Clara · posted 2026-10-28
- Etch Equipment Engineer - DaysSamsung · 12100 Samsung Blvd, Austin, TX, USA · posted 2026-10-28
- SRAM/ROM Circuit Design EngineerNXP Semiconductors · Austin (Oakhill, Office) · posted 2026-10-28
- Strategic Sourcing Manager, DC Infrastructure EquipmentOracle · Nashville, TN, United States; Austin, TX, United States · posted 2026-10-27
- Deputy Program Manager, ShipbuildingSaronic · Austin, TX · posted 2026-10-26
- Exam Development Program Manager, NetSuite CertificationOracle · United States; Canada; Austin, TX, United States +1 more · posted 2026-10-26
- Director Design EngineeringGlobalFoundries · Richardson; Austin · posted 2026-10-26
- Principal Mixed-Signal Design EngineerAnalog Devices · US, MA, Wilmington; Canada, Toronto; US, TX, Austin, Plaza on the Lake +2 more · posted 2026-10-26
- Silicon Design IP Licensing SpecialistNXP Semiconductors · Austin (Oakhill, Office) · posted 2026-10-23
- Electrical Build EngineerSaronic · Austin, TX · posted 2026-10-23
- CPU IP Design & Verification Intern – RISC-V Processor Development (Summer 2027)GlobalFoundries · USA - Texas - Austin; USA - California - Santa Clara · posted 2026-10-23
- Sr. IC Package Design Engineer (Silicon Engineering)SpaceX · Austin, TX · posted 2026-10-23
- GCS Gas Equipment EngineerSamsung · 12100 Samsung Blvd, Austin, TX, USA · posted 2026-10-23
- CPU IP Design & Verification Engineer – RISC-V (2027 New College Graduate)GlobalFoundries · USA - Texas - Austin; USA - California - Santa Clara · posted 2026-10-23
- Senior Director, Mergers & Acquisitions CounselNXP Semiconductors · Austin (Oakhill, Office) · posted 2026-10-23
- Static Timing Analysis Design Engineer / Physical DesignNXP Semiconductors · Austin (Oakhill, Office) · posted 2026-10-23
- Design Verification EngineerIntel · US, California, Santa Clara; US, Texas, Austin · posted 2026-10-22
- Senior Staff Engineer, Physical DesignMarvell · Austin, TX · posted 2026-10-22
- Photo Equipment EngineerSamsung · 12100 Samsung Blvd, Austin, TX, USA · posted 2026-10-22
- Mixed Signal Design Verification EngineerIntel · US, Oregon, Hillsboro; US, Texas, Austin · posted 2026-10-22
- Chip Lead / Physical Design DirectorCadence · AUSTIN 03; SAN JOSE · posted 2026-10-20
- Memory Circuit Design EngineerIntel · US, Texas, Austin · posted 2026-10-19
- Design Application EngineeringGlobalFoundries · OFFSITE - USA - California; Essex Junction; Austin +1 more · posted 2026-10-19
- Entry Level DFT Design EngineerNXP Semiconductors · Austin (Oakhill, Office) · posted 2026-10-19
- Senior Program Manager, Learning Content Programs NetSuiteOracle · United States; Canada; Austin, TX, United States +1 more · posted 2026-10-19
- Program Manager, Learning Content Programs-NetSuiteOracle · United States; Canada; Austin, TX, United States +1 more · posted 2026-10-18
- Principal Technical Program Manager - DTCO & Design Technology IntegrationIntel · US, Oregon, Hillsboro; US, California, Santa Clara; US, Texas, Austin · posted 2026-10-15
- Design ManagerSaronic · Austin, TX · posted 2026-10-15
- Senior ASIC Floorplan Design EngineerNVIDIA · US, CA, Santa Clara; US, TX, Austin · posted 2026-10-14
- Senior Design ManagerSaronic · Austin, TX · posted 2026-10-14
- Linux/Android Embedded Firmware DeveloperHP · Austin, Texas, United States of America · posted 2026-10-14
- Manager II, Operations Management (M2) 2nd Shift- MDP BuildApplied Materials · Austin,TX · posted 2026-10-14
- Senior Instructional DesignerSamsara · Remote - Austin; Remote - CA; Remote - Chicago; Remote - Dallas; Remote - Houston; Remote - Seattle · posted 2026-10-14
- Senior Analog/Mixed-Signal (AMS) Design Verification EngineerAnalog Devices · US, TX, Austin, Plaza on the Lake; US, NC, Durham · posted 2026-10-13
- Static Timing Analysis Design Engineer / Physical DesignNXP Semiconductors · Austin (Oakhill, Office) · posted 2026-10-13
- Technical Design Artist, Intern 2027Allen Control Systems · Austin, TX · posted 2026-10-13
- Static Timing Analysis Design Engineer / Physical DesignNXP Semiconductors · Austin (Oakhill, Office) · posted 2026-10-13
- Senior DTCO Engineer, CPU Physical DesignNVIDIA · US, CA, Santa Clara; US, TX, Austin; US, OR, Hillsboro · posted 2026-10-11
- Principal Software Development Engineer (IC4) - Network Region Build (NRB)Oracle · United States; Abilene, TX, United States; Austin, TX, United States +5 more · posted 2026-10-09
- SMTS ASIC Digital DesignGlobalFoundries · Austin; Netherlands · posted 2026-10-09
- Experienced Diffusion/Implant Flash and Laser Equipment EngineerSamsung · 12100 Samsung Blvd, Austin, TX, USA · posted 2026-10-09
- Digital IC Design Intern, MS - Summer 2027Marvell · Santa Clara, CA; Irvine, CA; Austin, TX +3 more · posted 2026-10-08
- CPU Physical Design EngineerIntel · US, Texas, Austin · posted 2026-10-08
- Distinguished Technologist - Enterprise Integration and Platform Native AIHP · Spring, Texas, United States of America; Austin, Texas, United States of America · posted 2026-10-08
- Group Product Manager - Labor and EquipmentProcore · US - Texas - Austin · posted 2026-10-07
- Staff Digital Design EngineerAnalog Devices · US, NC, Durham; US, TX, Austin, Plaza on the Lake · posted 2026-10-07
- Group Director, Design Engineering - Front EndCadence · AUSTIN · posted 2026-10-06
- Senior Mask Layout Design EngineerNVIDIA · US, CA, Santa Clara; US, TX, Austin · posted 2026-10-06
- PCIe Design Verification Intern - Summer 2027NVIDIA · US, TX, Austin · posted 2026-10-06
- Lead Design EngineerCadence · AUSTIN · posted 2026-10-01
- Principal Design EngineerCadence · AUSTIN · posted 2026-10-01
- Processor Core Logic Design/ArchitectCadence · AUSTIN · posted 2026-10-01
- Principal Design EngineerCadence · AUSTIN · posted 2026-10-01
- Build Systems Engineer2K · Austin, Texas, United States · posted 2026-10-01
- Sr. ASIC Design Engineer (Silicon Engineering)SpaceX · Austin, TX · posted 2026-09-30
- Senior Physical Design EngineerNVIDIA · US, CA, Santa Clara; US, TX, Austin · posted 2026-09-29
- Principal Physical Design EngineerNXP Semiconductors · Austin (Oakhill, Office) · posted 2026-09-29
- Digital IC Design Intern, BS - Summer 2027Marvell · Santa Clara, CA; Irvine, CA; Austin, TX +2 more · posted 2026-09-29
- Senior Physical Design and Timing EngineerNVIDIA · US, CA, Santa Clara; US, TX, Austin; US, OR, Hillsboro +1 more · posted 2026-09-29
- Package Design Methodology EngineerNVIDIA · US, CA, Santa Clara; US, TX, Austin; US, CA, Remote · posted 2026-09-29
- Cryo RFIC Design Engineer, QuantumGlobalFoundries · Austin; Santa Clara · posted 2026-09-28
- Semiconductor Equipment Order Management IVApplied Materials · Austin,TX · posted 2026-09-28
- Cryo CMOS Analog Design EngineerGlobalFoundries · Austin; Santa Clara · posted 2026-09-28
- CryoCMOS Digital IC Design engineer, QuantumGlobalFoundries · Austin; Santa Clara · posted 2026-09-28
- CryoCMOS Digital IC Design Engineer, QuantumGlobalFoundries · Austin; Santa Clara · posted 2026-09-28
- Circuit Design Intern, Master's or PhD (Summer 2027)GlobalFoundries · USA - Texas - Austin · posted 2026-09-28
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