Director, Frontend Design Enablement

The Director of Front-End Design Enablement is responsible for leading a centralized team that defines, develops, deploys, and continuously advances the common tools, flows, methodologies, and platforms for Functional Verification and SoC Integration across NXP IPs, subsystems, and SoCs.

The organization will establish and drive adoption of common engineering solutions that reduce fragmentation and duplication, improve reuse and automation, and provide consistent ways of working across product development teams.

The Director will focus on two core areas:

• Functional Verification
• SoC Integration

The mission is to enable higher engineering productivity, improved product quality, greater reuse, and faster time-to-market through standardized and scalable front-end design capabilities.

A key responsibility is also to drive the next generation of engineering workflows, leveraging AI agents, agentic workflows, intelligent automation, and engineering data to transform how engineers interact with design environments and EDA tools.

Key Responsibilities

1. Front-End Design Enablement Strategy

Drive the deployment strategy and technology roadmap for Functional Verification and SoC Integration.

• Work with key functional leads to establish a common vision and architecture for front-end design enablement.
• Drive convergence toward common tools, common flows, and common methodologies across NXP.
• Establish scalable reference flows supporting IP → subsystem → SoC development.
• Reduce unnecessary duplication of locally developed tools, scripts, and methodologies.
• Enable reuse of engineering solutions across projects and business organizations.
• Balance standardization with controlled extensibility for legitimate product-specific requirements.
• Establish multi-year roadmaps aligned with increasing IP and SoC complexity.

2. Functional Verification Enablement

Lead the deployment, adoption, and evolution of common Functional Verification tools, flows, and methodologies.

Key areas include:

• SystemVerilog/UVM verification
• Simulation and debug
• Verification planning
• Coverage-driven verification
• Assertion-based verification
• Formal verification
• Verification IP and reusable verification components
• Regression management and automation
• Verification closure
• Hardware/software co-verification
• Emulation and acceleration integration
• Verification analytics and dashboards

Drive verification architectures and methodologies that maximize reuse across:

Drive shift-left verification by identifying design and integration issues as early as practical, reducing expensive late-cycle debug and rework.

3. SoC Integration Enablement

Lead deployment and adoption of common SoC Integration tools, flows, and methodologies supporting increasingly complex NXP products.

Key areas include:

• IP configuration and assembly
• IP and subsystem integration
• Interface and connectivity management
• Register and memory-map integration
• Clock and reset integration
• Configuration management and consistency
• Integration validation
• IP metadata and machine-readable design information
• Automated generation and checking
• Hierarchical integration across IP, subsystem, and SoC
• Integration readiness and quality checks

4. AI Agents, Agentic Workflows and New Ways of Working

The Director will play a key role in transforming traditional design enablement through AI-enabled engineering and agentic workflows.

The objective is not simply to add AI features to existing flows. The organization should use AI to rethink how verification and integration work is performed.

5. EDA Technology and Partner Strategy

Drive strategic engagement with key EDA technology providers such as Synopsys, Cadence, and Siemens EDA, as appropriate.

Responsibilities include:

• Technology evaluation and benchmarking
• Tool qualification
• Technology roadmap alignment
• Strategic technical engagement
• Introduction of new EDA technologies
• Rationalization and consolidation of overlapping solutions
• Joint innovation and proof-of-concept activities
• Integration of emerging AI capabilities into front-end flows

Ensure that technology investments support the broader objective of commonality, interoperability, automation, scalability, and engineering productivity.

Required Qualifications

• Bachelor's or master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
• Extensive experience in semiconductor, ASIC, or SoC development.
• Significant experience in functional verification, SoC integration, EDA/design enablement, or related disciplines.
• Deep understanding of several of the following:
  • RTL design
  • SystemVerilog/UVM
  • Simulation and debug
  • Formal verification
  • Verification planning and coverage
  • Verification IP
  • IP/subsystem/SoC integration
  • SoC architecture and connectivity
  • Design and verification automation
  • EDA infrastructure
• Strong understanding of major commercial EDA ecosystems.
• Experience driving common solutions across multiple engineering organizations.
• Demonstrated ability to lead complex technology and methodology transformation.
• Strong leadership, communication, and stakeholder-management capabilities.

Preferred Qualifications

• Advanced degree in EE, CE, CS, or related discipline.
• Experience supporting complex IP and SoC development.
• Experience defining enterprise-scale verification or SoC-integration methodologies.
• Experience establishing common EDA platforms across multiple development organizations.
• Experience strategically engaging with major EDA suppliers.
• Experience with AI/ML, generative AI, LLMs, AI agents, or agentic workflows applied to semiconductor engineering.
• Experience driving major engineering methodology and organizational change.

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